{"id":2880,"date":"2011-03-08T13:44:33","date_gmt":"2011-03-08T04:44:33","guid":{"rendered":"http:\/\/mkusunoki.net\/?p=2880"},"modified":"2013-12-06T22:02:43","modified_gmt":"2013-12-06T13:02:43","slug":"%e3%81%a8%e3%82%8a%e3%81%82%e3%81%88%e3%81%9a%e3%80%81fpga%e7%89%88-hello-world","status":"publish","type":"post","link":"https:\/\/mkusunoki.net\/?p=2880","title":{"rendered":"\u3068\u308a\u3042\u3048\u305a\u3001FPGA\u7248 Hello, World"},"content":{"rendered":"

\"\"<\/a><\/p>\n

\u666e\u6bb5 DWM\u3068\u304b\u8aad\u307e\u306a\u3044\u3093\u3067\u3001CPLD\u3084FPGA\u306e\u4e8b\u60c5\u306f\u3055\u3063\u3071\u308a\u308f\u304b\u308a\u307e\u305b\u3093\u3002\u6614\u306e\u30da\u30fc\u30b8\u306b XILINX XC9500\u30b7\u30ea\u30fc\u30ba\u306e
\nCPLD\u4f7f\u3063\u305f\u8a18\u4e8b\u3082\u66f8\u304d\u307e\u3057\u305f\u304c2002\u5e746\u6708\u306e\u3053\u3068\u3067\u3001\u5f53\u7136\u3053\u3053\u306e\u30b5\u30a4\u30c8\u306b\u306f\u63b2\u8f09\u3057\u3066\u307e\u305b\u3093\u3002
\n\u4eca\u66f4\u3068\u3044\u3046\u611f\u3058\u306f\u3042\u308b\u306e\u3067\u3059\u304c\u3001\u4e45\u3057\u3076\u308a\u306b\u3084\u3063\u3066\u307f\u305f\u304f\u306a\u3063\u305f\u306e\u3067\u5165\u9580\u30ad\u30c3\u30c8\u3092\u8cb7\u3063\u3066\u30dc\u30c1\u30dc\u30c1\u904a\u3073\u305f\u3044\u3068\u601d\u3044\u307e\u3059\u3002<\/p>\n

FPGA\u306e\u300cHello, World\u300d\u306f\u3001\u306f\u3084\u308a LED\u30d4\u30b3\u30d4\u30b3\u3067\u3059\u304c\u3001\u4eca\u56de\u306f\u98db\u3070\u3057\u3066 VGA \u51fa\u529b\u306e\u7df4\u7fd2\u3067\u3059\u3002
\nVerilog HDL\u5165\u9580\u672c\u898b\u306a\u304c\u3089\u66f8\u3044\u3066\u307f\u307e\u3057\u305f\u3002\u4ee5\u4e0b\u30bd\u30fc\u30b9\u3068UCF\u3067\u3059\u3002
\nWebpack 10.1\u3067\u4f5c\u6210\u3057\u3066\u3068\u308a\u3042\u3048\u305a\u6210\u529f\u3063\u3068<\/p>\n

\"\"<\/a>
\n\"\"<\/a><\/p>\n

\u30e2\u30cb\u30bf\u306fPC\u30c7\u30dd\u5e97\u982d\u306b\u7a4d\u3093\u3067\u3042\u3063\u305f\u30bb\u30ea\u30f3\u30b0 KW-M80C \u3068\u3044\u3046\u3068\u3053\u306eSVGA\u30e2\u30cb\u30bf\u3067\u30a2\u30ca\u30ed\u30b0RGB\u3068\u30b3\u30f3\u30dd\u30c3\u30b8\u30c8\u5165\u529b\u3060\u3051\u306e
\n\u30b7\u30f3\u30d7\u30eb\u69cb\u6210\u3067\u3059\u30021\u4e074\u5343\u5186\u304f\u3089\u3044\u3060\u3063\u305f\u3068\u601d\u3044\u307e\u3059\u3002\u307e\u3041\u3061\u3087\u3063\u3068\u4f7f\u3046\u7a0b\u5ea6\u306a\u3089\u4f7f\u3048\u308b\u30e2\u30cb\u30bf\u3067\u3059\u3002<\/p>\n

\r\n`timescale 1ns \/ 1ps\r\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\r\n\/\/ Company:\r\n\/\/ Engineer:\r\n\/\/\r\n\/\/ Create Date:    12:46:33 06\/22\/2008\r\n\/\/ Design Name:\r\n\/\/ Module Name:    vga\r\n\/\/ Project Name:\r\n\/\/ Target Devices:\r\n\/\/ Tool versions:\r\n\/\/ Description:\r\n\/\/\r\n\/\/ Dependencies:\r\n\/\/\r\n\/\/ Revision:\r\n\/\/ Revision 0.01 - File Created\r\n\/\/ Additional Comments:\r\n\/\/\r\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\r\n\/\/\r\n\/\/ -- \u6c34\u5e73\u30bf\u30a4\u30df\u30f3\u30b0 --\r\n\/\/ \u8868\u793a\u671f\u9593:   640\u30c9\u30c3\u30c8\r\n\/\/ \u30d5\u30ed\u30f3\u30c8\u30dd\u30fc\u30c1:  16\u30c9\u30c3\u30c8\r\n\/\/ \u6c34\u5e73\u540c\u671f:    96\u30c9\u30c3\u30c8(656)\r\n\/\/ \u30d0\u30c3\u30af\u30dd\u30fc\u30c1:   48\u30c9\u30c3\u30c8(752)\r\n\/\/\r\n\/\/ -- \u5782\u76f4\u30bf\u30a4\u30df\u30f3\u30b0 --\r\n\/\/ \u8868\u793a\u671f\u9593:   480\u30e9\u30a4\u30f3\r\n\/\/ \u30d5\u30ed\u30f3\u30c8\u30dd\u30fc\u30c1:  10\u30e9\u30a4\u30f3\r\n\/\/ \u5782\u76f4\u540c\u671f:     2\u30e9\u30a4\u30f3(490)\r\n\/\/ \u30d0\u30c3\u30af\u30dd\u30fc\u30c1:   29\u30e9\u30a4\u30f3(492)\r\n\r\nmodule vga(CLK_50MHZ, VGA_R, VGA_G, VGA_B, VGA_HSYNC, VGA_VSYNC);\r\n\r\ninput CLK_50MHZ;\r\noutput [3:0] VGA_R;\r\noutput [3:0] VGA_G;\r\noutput [3:0] VGA_B;\r\noutput VGA_HSYNC;\r\noutput VGA_VSYNC;\r\n\r\nreg [3:0] VGA_R;\r\nreg [3:0] VGA_G;\r\nreg [3:0] VGA_B;\r\nreg VGA_HSYNC;\r\nreg VGA_VSYNC;\r\n\r\nwire clk_25mhz;\r\nreg clk_25mhz_a;\r\nassign clk_25mhz = clk_25mhz_a;\r\n\r\nreg [9:0] hcount;\r\nreg [9:0] vcount;\r\n\r\n\/* 25MHz \u306e\u30af\u30ed\u30c3\u30af\u4f5c\u6210 *\/\r\nalways @(posedge CLK_50MHZ)\r\nbegin\r\nclk_25mhz_a &lt;= \u203eclk_25mhz_a;\r\nend\r\n\r\n\/* 25Mhz \u306e\u30af\u30ed\u30c3\u30af\u3067\u753b\u9762\u63cf\u753b *\/\r\nalways @(posedge clk_25mhz)\r\nbegin\r\n\r\n\/\/ \u6c34\u5e73\u30bf\u30a4\u30df\u30f3\u30b0\r\nhcount &lt;= hcount + 1;     \/\/ \u6c34\u5e73\u30ab\u30a6\u30f3\u30c8 800 \u3067\u4e00\u5468     if(hcount &gt; 10'd799)\r\nbegin\r\nhcount &lt;= 0;\r\nvcount &lt;= vcount + 1;\r\nend\r\n\/\/ \u6c34\u5e73\u540c\u671f\u51fa\u529b\r\nif(hcount == 10'd655)\r\nbegin\r\nVGA_HSYNC &lt;= 0;\r\nVGA_R &lt;= 4'b0000;\r\nVGA_G &lt;= 4'b0000;\r\nVGA_B &lt;= 4'b0000;\r\nend\r\n\/\/ \u6c34\u5e73\u540c\u671f\u51fa\u529b\u7d42\u4e86\r\nif(hcount == 10'd751)\r\nbegin\r\nVGA_HSYNC &lt;= 1;     end     \/\/ \u5782\u76f4\u30bf\u30a4\u30df\u30f3\u30b0     \/\/ 521 \u30e9\u30a4\u30f3\u3067\u4e00\u5468     if(vcount &gt; 10'd520)\r\nbegin\r\nvcount &lt;= 0;\r\nend\r\n\/\/ \u5782\u76f4\u540c\u671f\u958b\u59cb\r\nif(vcount == 10'd489)\r\nbegin\r\nVGA_VSYNC &lt;= 0;\r\nend\r\n\/\/ \u5782\u76f4\u540c\u671f\u7d42\u4e86\r\nif(vcount == 10'd491)\r\nbegin\r\nVGA_VSYNC &lt;= 1;\r\nend\r\n\r\n\/\/ \u30ab\u30e9\u30fc\u30d0\u30fc\u3082\u3069\u304d \u2192 \u30e1\u30e2\u30ea\u30a4\u30f3\u30bf\u30d5\u30a7\u30fc\u30b9\u306b\u3059\u308b\r\nif(hcount == 10'd0)\r\nbegin\r\nVGA_R &lt;= 4'b1111;\r\nVGA_G &lt;= 4'b1111;\r\nVGA_B &lt;= 4'b1111;\r\nend\r\nif(hcount == 10'd79)\r\nbegin\r\nVGA_R &lt;= 4'b0000;\r\nVGA_G &lt;= 4'b1111;\r\nVGA_B &lt;= 4'b1111;\r\nend\r\nif(hcount == 10'd159)\r\nbegin\r\nVGA_R &lt;= 4'b1111;\r\nVGA_G &lt;= 4'b0000;\r\nVGA_B &lt;= 4'b1111;\r\nend\r\nif(hcount == 10'd239)\r\nbegin\r\nVGA_R &lt;= 4'b1111;\r\nVGA_G &lt;= 4'b1111;\r\nVGA_B &lt;= 4'b0000;\r\nend\r\nif(hcount == 10'd319)\r\nbegin\r\nVGA_R &lt;= 4'b1111;\r\nVGA_G &lt;= 4'b0000;\r\nVGA_B &lt;= 4'b0000;\r\nend\r\nif(hcount == 10'd399)\r\nbegin\r\nVGA_R &lt;= 4'b0000;\r\nVGA_G &lt;= 4'b1111;\r\nVGA_B &lt;= 4'b0000;\r\nend\r\nif(hcount == 10'd479)\r\nbegin\r\nVGA_R &lt;= 4'b0000;\r\nVGA_G &lt;= 4'b0000;\r\nVGA_B &lt;= 4'b1111;\r\nend\r\nif(hcount == 10'd559)\r\nbegin\r\nVGA_R &lt;= 4'b0000;\r\nVGA_G &lt;= 4'b0000;\r\nVGA_B &lt;= 4'b0000;\r\nend\r\n\r\nend\r\nendmodule\r\n\r\n&nbsp;\r\n<pre><code>\r\n\r\nNET "VGA_R&lt;3&gt;" LOC = "C8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_R&lt;2&gt;" LOC = "B8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_R&lt;1&gt;" LOC = "B3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_R&lt;0&gt;" LOC = "A3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_G&lt;3&gt;" LOC = "D6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_G&lt;2&gt;" LOC = "C6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_G&lt;1&gt;" LOC = "D5" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_G&lt;0&gt;" LOC = "C5" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_B&lt;3&gt;" LOC = "C9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_B&lt;2&gt;" LOC = "B9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_B&lt;1&gt;" LOC = "D7" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_B&lt;0&gt;" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_HSYNC" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "VGA_VSYNC" LOC = "B11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;\r\n\r\nNET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;\r\n\r\n# NET "CLK_AUX" LOC = "V12"| IOSTANDARD = LVCMOS33 ;\r\n\r\n# NET "CLK_SMA" LOC = "U12"| IOSTANDARD = LVCMOS33 ;\r\n\r\n<\/pre>\n
<\/code>
\n\u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"
\u666e\u6bb5 DWM\u3068\u304b\u8aad\u307e\u306a\u3044\u3093\u3067\u3001CPLD\u3084FPGA\u306e\u4e8b\u60c5\u306f\u3055\u3063\u3071\u308a\u308f\u304b\u308a\u307e\u305b\u3093\u3002\u6614\u306e\u30da\u30fc\u30b8\u306b XILINX XC9500\u30b7\u30ea\u30fc\u30ba\u306e CPLD\u4f7f\u3063\u305f\u8a18\u4e8b\u3082\u66f8\u304d\u307e\u3057\u305f\u304c2002\u5e746\u6708\u306e\u3053\u3068\u3067\u3001\u5f53\u7136\u3053\u3053\u306e\u30b5\u30a4\u30c8\u306b\u306f\u63b2\u8f09\u3057\u3066\u307e\u305b\u3093 … “\u3068\u308a\u3042\u3048\u305a\u3001FPGA\u7248 Hello, World” \u306e<\/span>\u7d9a\u304d\u3092\u8aad\u3080<\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[7],"tags":[201,205,44],"class_list":["post-2880","post","type-post","status-publish","format-standard","hentry","category-kousaku","tag-fpga","tag-spartan-3","tag-xilinx-2"],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/posts\/2880","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2880"}],"version-history":[{"count":0,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/posts\/2880\/revisions"}],"wp:attachment":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2880"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2880"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2880"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}