{"id":2877,"date":"2011-03-07T15:00:48","date_gmt":"2011-03-07T06:00:48","guid":{"rendered":"http:\/\/mkusunoki.net\/?p=2877"},"modified":"2013-12-06T22:03:00","modified_gmt":"2013-12-06T13:03:00","slug":"spartan-3a-dcm-%e3%82%92-veritak-%e3%81%a7%e5%8b%95%e4%bd%9c%e7%a2%ba%e8%aa%8d%e3%81%97%e3%81%a6%e3%81%bf%e3%81%9f%e3%80%82","status":"publish","type":"post","link":"https:\/\/mkusunoki.net\/?p=2877","title":{"rendered":"Spartan-3A DCM \u3092 veritak \u3067\u52d5\u4f5c\u78ba\u8a8d\u3057\u3066\u307f\u305f\u3002"},"content":{"rendered":"<p>\nSpartan-3A \u30b9\u30bf\u30fc\u30bf\u30fc\u30ad\u30c3\u30c8\u306e PDF \u306e\u8cc7\u6599\u3084\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u30ce\u30fc\u30c8\u306a\u3069\u898b\u3066\u307e\u3059\u304c<br \/>\n\u57fa\u672c\u30af\u30ed\u30c3\u30af\u306f\u300150MHz\u306e\u6c34\u6676\u304c\u539f\u767a\u3067\u3059\u304c\u3001\u305d\u308c\u4ee5\u5916\u306e<br \/>\n\u30af\u30ed\u30c3\u30af\u304c\u6b32\u3057\u3044\u3068\u304d\u306f\u3001DCM(Digital Clock Manager)\u3092\u4f7f\u7528\u3059\u308b\u3088\u3046\u3067\u3059\u3002<br \/>\n\u3068\u3044\u3046\u3053\u3068\u3067\u3001DCM \u3092\u4f7f\u7528\u3059\u308b\u6e96\u5099\u3068\u3057\u3066 veritak \u3067\u78ba\u8a8d\u3057\u3066\u307f\u307e\u3057\u305f\u3002\n<\/p>\n<ul>\n<li>CORE Generator \u3067 DCM \u306e\u30b3\u30fc\u30c9\u3092 GUI \u3067\u751f\u6210\n<\/li>\n<li>\u30c6\u30b9\u30c8\u7528\u306e Verilog \u30b3\u30fc\u30c9\u3092\u66f8\u3044\u3066\u307f\u308b\n<\/li>\n<li>veritak(\u30b7\u30a7\u30a2\u30a6\u30a7\u30a2\u7248)\u3067\u30b7\u30df\u30e5\u30fc\u30ec\u30fc\u30b7\u30e7\u30f3\u3057\u3066\u307f\u308b\n<\/li>\n<\/ul>\n<p>\nCORE Generator \u3092\u8d77\u52d5\u3057\u3066 DCM \u306e\u30b3\u30a2\u3092\u4f5c\u6210\u3057\u3066\u307f\u307e\u3057\u305f\u3002<br \/>\n\u4eca\u56de\u306f\u3001 FPGA Features and Design -> Clocking -> Spartan-3E, Spartan-3A -> Single DCM_SP<br \/>\n\u3068\u30d5\u30a1\u30f3\u30af\u30b7\u30e7\u30f3\u3092\u9078\u629e\u3057\u3066\u3001DCM\u4f5c\u6210\u3067\u3059\u3002<br \/>\n\u4eca\u56de\u306f\u3001CLK0\u4ee5\u5916\u306b\u300190\u5ea6\u3065\u3064\u4f4d\u76f8\u305a\u308c\u305f CLK90, CLK180, CLK270 \u306a\u3069\u3082<br \/>\n\u51fa\u529b\u3059\u308b\u3088\u3046\u306b\u3057\u3066\u307f\u307e\u3057\u305f\u3002\n<\/p>\n<p>\n\u307e\u305f\u3001PDF \u6587\u66f8\u306b\u3042\u3063\u305f\u63a8\u5968\u30ea\u30bb\u30c3\u30c8\u56de\u8def(\u30b7\u30d5\u30c8\u30ec\u30b8\u30b9\u30bf\u3067\u30ef\u30f3\u30b7\u30e7\u30c3\u30c8\u30d1\u30eb\u30b9\u3092\u51fa\u3059)\u3082\u8ffd\u52a0\u3057\u307e\u3057\u305f\u3002\n<\/p>\n<p>\n\u751f\u6210\u3055\u308c\u305f DCM \u30e2\u30b8\u30e5\u30fc\u30eb\n<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\r\n\/\/ Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.\r\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\r\n\/\/   ____  ____ \r\n\/\/  \/   \/\\\/   \/ \r\n\/\/ \/___\/  \\  \/    Vendor: Xilinx \r\n\/\/ \\   \\   \\\/     Version : 10.1.03\r\n\/\/  \\   \\         Application : xaw2verilog\r\n\/\/  \/   \/         Filename : dcm_test01.v\r\n\/\/ \/___\/   \/\\     Timestamp : 04\/21\/2009 13:34:03\r\n\/\/ \\   \\  \/  \\ \r\n\/\/  \\___\\\/\\___\\ \r\n\/\/\r\n\/\/Command: xaw2verilog -st C:\\mkusunoki\\\\dcm_test01.xaw C:\\mkusunoki\\\\dcm_test01\r\n\/\/Design Name: dcm_test01\r\n\/\/Device: xc3s700a-4fg484\r\n\/\/\r\n\/\/ Module dcm_test01\r\n\/\/ Generated by Xilinx Architecture Wizard\r\n\/\/ Written for synthesis tool: XST\r\n`timescale 1ns \/ 1ps\r\n\r\nmodule dcm_test01(CLKFB_IN, \r\n                  CLKIN_IN, \r\n                  RST_IN, \r\n                  CLKIN_IBUFG_OUT, \r\n                  CLK0_OUT, \r\n                  CLK90_OUT, \r\n                  CLK180_OUT, \r\n                  CLK270_OUT, \r\n                  LOCKED_OUT);\r\n\r\n    input CLKFB_IN;\r\n    input CLKIN_IN;\r\n    input RST_IN;\r\n   output CLKIN_IBUFG_OUT;\r\n   output CLK0_OUT;\r\n   output CLK90_OUT;\r\n   output CLK180_OUT;\r\n   output CLK270_OUT;\r\n   output LOCKED_OUT;\r\n   \r\n   wire CLKFB_IBUFG;\r\n   wire CLKIN_IBUFG;\r\n   wire CLK0_BUF;\r\n   wire CLK90_BUF;\r\n   wire CLK180_BUF;\r\n   wire CLK270_BUF;\r\n   wire GND_BIT;\r\n   \r\n   assign GND_BIT = 0;\r\n   assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;\r\n   IBUFG CLKFB_IBUFG_INST (.I(CLKFB_IN), \r\n                           .O(CLKFB_IBUFG));\r\n   IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), \r\n                           .O(CLKIN_IBUFG));\r\n   BUFG CLK0_BUFG_INST (.I(CLK0_BUF), \r\n                        .O(CLK0_OUT));\r\n   BUFG CLK90_BUFG_INST (.I(CLK90_BUF), \r\n                         .O(CLK90_OUT));\r\n   BUFG CLK180_BUFG_INST (.I(CLK180_BUF), \r\n                          .O(CLK180_OUT));\r\n   BUFG CLK270_BUFG_INST (.I(CLK270_BUF), \r\n                          .O(CLK270_OUT));\r\n   DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IBUFG), \r\n                       .CLKIN(CLKIN_IBUFG), \r\n                       .DSSEN(GND_BIT), \r\n                       .PSCLK(GND_BIT), \r\n                       .PSEN(GND_BIT), \r\n                       .PSINCDEC(GND_BIT), \r\n                       .RST(RST_IN), \r\n                       .CLKDV(), \r\n                       .CLKFX(), \r\n                       .CLKFX180(), \r\n                       .CLK0(CLK0_BUF), \r\n                       .CLK2X(), \r\n                       .CLK2X180(), \r\n                       .CLK90(CLK90_BUF), \r\n                       .CLK180(CLK180_BUF), \r\n                       .CLK270(CLK270_BUF), \r\n                       .LOCKED(LOCKED_OUT), \r\n                       .PSDONE(), \r\n                       .STATUS());\r\n   defparam DCM_SP_INST.CLK_FEEDBACK = &quot;1X&quot;;\r\n   defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;\r\n   defparam DCM_SP_INST.CLKFX_DIVIDE = 1;\r\n   defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;\r\n   defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = &quot;FALSE&quot;;\r\n   defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;\r\n   defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = &quot;NONE&quot;;\r\n   defparam DCM_SP_INST.DESKEW_ADJUST = &quot;SYSTEM_SYNCHRONOUS&quot;;\r\n   defparam DCM_SP_INST.DFS_FREQUENCY_MODE = &quot;LOW&quot;;\r\n   defparam DCM_SP_INST.DLL_FREQUENCY_MODE = &quot;LOW&quot;;\r\n   defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = &quot;TRUE&quot;;\r\n   defparam DCM_SP_INST.FACTORY_JF = 16&#039;hC080;\r\n   defparam DCM_SP_INST.PHASE_SHIFT = 0;\r\n   defparam DCM_SP_INST.STARTUP_WAIT = &quot;FALSE&quot;;\r\nendmodule\r\n<\/pre>\n<p>\n\u4f5c\u6210\u3057\u3066\u307f\u305f\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\n<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\n`default_nettype none\r\n`timescale 1ns \/ 1ns\r\n\r\nmodule dcm_test01_testbench;\r\n\r\nreg CLK50MHz;\r\nreg RST_IN;\r\nwire CLKIN_IBUFG_OUT;\r\nwire CLK0_OUT;\r\nwire CLK90_OUT;\r\nwire CLK180_OUT;\r\nwire CLK270_OUT;\r\nwire LOCKED_OUT;\r\n\r\ndcm_test01 dcm01 (\r\n\t.CLKFB_IN(CLK0_OUT),\r\n\t.CLKIN_IN(CLK50MHz),\r\n\t.RST_IN(Q),\r\n\t.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),\r\n\t.CLK0_OUT(CLK0_OUT),\r\n\t.CLK90_OUT(CLK90_OUT),\r\n\t.CLK180_OUT(CLK180_OUT),\r\n\t.CLK270_OUT(CLK270_OUT),\r\n\t.LOCKED_OUT(LOCKED_OUT)\r\n\t);\r\n\r\nwire Q;\r\n\/\/defparam U1.INIT = 16&#039;h000F;\r\nSRL16 #(16&#039;h000F) U1 (\r\n\t.Q(Q),\r\n\t.A0(1),\r\n\t.A1(1),\r\n\t.A2(1),\r\n\t.A3(1),\r\n\t.CLK(CLK50MHz),\r\n\t.D(0)\r\n);\r\n\r\n\/\/ \u30af\u30ed\u30c3\u30af\r\ninitial\r\nbegin\r\n\tCLK50MHz = 0;\r\n\tforever #10 CLK50MHz = ~CLK50MHz;\r\nend\r\n\r\ninitial\r\nbegin\r\n\t#1600\r\n\t$finish;\r\nend\r\n\r\nalways\r\n\t$monitor($time, &quot;clkin=%b reset=%b clk0=%b clk90=%b clk180=%b clk270=%b locked=%b\\n&quot;, CLK50MHz, RST_IN,CLK0_OUT,CLK90_OUT,CLK180_OUT,CLK270_OUT,LOCKED_OUT);\r\nendmodule\r\n<\/pre>\n<p>\n\u3067\u3001veritak\u3067\u30b7\u30df\u30e5\u30fc\u30ec\u30fc\u30b7\u30e7\u30f3\u3057\u3066\u307f\u307e\u3057\u305f\u3068\u3053\u308d\u3001\u5404\u7a2e\u30af\u30ed\u30c3\u30af\u3068\u3001\u30ea\u30bb\u30c3\u30c8\u306b\u53cd\u5fdc\u3059\u308b\u3053\u3068\u3001\u3068<br \/>\n\u30af\u30ed\u30c3\u30af\u306e\u30ed\u30c3\u30af\u72b6\u614b\u3082\u8868\u793a\u3055\u308c\u305f\u306e\u3067\u5b9f\u969b\u306b\u30a4\u30f3\u30d7\u30ea\u3059\u308b\u5834\u5408\u3082\u3061\u3087\u3063\u3068\u5b89\u5fc3\u3068\u3044\u3046\u3053\u3068\u3067<\/p>\n<p><a href=\"http:\/\/mkusunoki.net\/?attachment_id=406\" rel=\"attachment wp-att-406\"><img loading=\"lazy\" decoding=\"async\" src=\"http:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DCM0001.png\" alt=\"\" title=\"S3ASK_DCM0001\" width=\"1054\" height=\"631\" class=\"alignnone size-full wp-image-406\" srcset=\"https:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DCM0001.png 1054w, https:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DCM0001-320x191.png 320w, https:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DCM0001-1024x613.png 1024w\" sizes=\"auto, (max-width: 709px) 85vw, (max-width: 909px) 67vw, (max-width: 1362px) 62vw, 840px\" \/><\/a><\/p>\n<p>\n\u306b\u3057\u3066\u3082\u3001\u3064\u3044\u3067\u3067 DDR2 SDRAM \u3082 MIG \u3067\u4f5c\u6210\u3057\u3066\u307f\u3066 veritak \u3057\u3066\u307f\u307e\u3057\u305f\u3068\u3053\u308d<br \/>\n\u3053\u308c\u3082\u52d5\u304d\u305d\u3046\u306a\u611f\u3058\u3067\u306f\u3042\u308a\u307e\u3059\u3002\u304c\u3001UG086 \u306b\u66f8\u3044\u3066\u308b\u4f7f\u3044\u304b\u305f\u304c<br \/>\n\u307e\u3060\u3088\u304f\u7406\u89e3\u51fa\u6765\u306a\u3044\u306e\u3068\u3001DDR\/DDR2 \u306a SDRAM \u306e\u57fa\u672c\u3082\u308f\u304b\u3063\u3066\u306a\u3044\u306e\u3067<br \/>\n\u3053\u308c\u304b\u3089\u4f59\u88d5\u304c\u51fa\u6765\u308c\u3070\u3001\u4f7f\u3063\u3066\u307f\u305f\u3044\u3067\u3059\u306d\u3002<br \/>\n\u3068\u308a\u3042\u3048\u305a\u3001picoblaze \u3092\u5148\u306b\u4f7f\u7528\u3057\u305f\u3044\u3067\u3059\u3002\n<\/p>\n<p><a href=\"http:\/\/mkusunoki.net\/?attachment_id=407\" rel=\"attachment wp-att-407\"><img loading=\"lazy\" decoding=\"async\" src=\"http:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DDR2_0001.png\" alt=\"\" title=\"S3ASK_DDR2_0001\" width=\"1054\" height=\"631\" class=\"alignnone size-full wp-image-407\" srcset=\"https:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DDR2_0001.png 1054w, https:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DDR2_0001-320x191.png 320w, https:\/\/mkusunoki.net\/wp\/wp-content\/uploads\/2011\/03\/S3ASK_DDR2_0001-1024x613.png 1024w\" sizes=\"auto, (max-width: 709px) 85vw, (max-width: 909px) 67vw, (max-width: 1362px) 62vw, 840px\" \/><\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Spartan-3A \u30b9\u30bf\u30fc\u30bf\u30fc\u30ad\u30c3\u30c8\u306e PDF \u306e\u8cc7\u6599\u3084\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u30ce\u30fc\u30c8\u306a\u3069\u898b\u3066\u307e\u3059\u304c \u57fa\u672c\u30af\u30ed\u30c3\u30af\u306f\u300150MHz\u306e\u6c34\u6676\u304c\u539f\u767a\u3067\u3059\u304c\u3001\u305d\u308c\u4ee5\u5916\u306e \u30af\u30ed\u30c3\u30af\u304c\u6b32\u3057\u3044\u3068\u304d\u306f\u3001DCM(Digital Clock Man &hellip; <a href=\"https:\/\/mkusunoki.net\/?p=2877\" class=\"more-link\"><span class=\"screen-reader-text\">&#8220;Spartan-3A DCM \u3092 veritak \u3067\u52d5\u4f5c\u78ba\u8a8d\u3057\u3066\u307f\u305f\u3002&#8221; \u306e<\/span>\u7d9a\u304d\u3092\u8aad\u3080<\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[7],"tags":[201,205,44],"class_list":["post-2877","post","type-post","status-publish","format-standard","hentry","category-kousaku","tag-fpga","tag-spartan-3","tag-xilinx-2"],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/posts\/2877","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2877"}],"version-history":[{"count":0,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=\/wp\/v2\/posts\/2877\/revisions"}],"wp:attachment":[{"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2877"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2877"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mkusunoki.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2877"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}